One embodiment of the present invention relates to memory devices. In particular, one embodiment of the present invention relates to self-timed blocks in synchronously controlled semiconductor memory devices.
Memory structures have become integral parts of modern VLSI systems, including digital line processing systems. Although typically it is desirable to incorporate as many memory cells as possible into a given area, memory cell density is usually constrained by other design factors such as layout efficiency, performance, power requirements, and noise sensitivity.
In view of the trends toward compact, high-performance, high-bandwidth integrated computer networks, portable computing, and mobile communications, the aforementioned constraints can impose severe limitations upon memory structure designs, which traditional memory systems and subcomponent implementations may fail to obviate.
One type of basic storage element is the static random access memory (hereinafter referred to as “SRAM”), which retains its memory state as long as power is applied to the cell. In one embodiment of a SRAM device, the memory state is usually stored as a voltage differential within a bistable functional element, such as an inverter loop.
A SRAM cell is comparatively more complex than a counterpart dynamic RAM (hereinafter referred to as “DRAM”), requiring more constituent elements, preferably transistors. Accordingly, DRAM devices require refreshing, thus commonly consume more power and dissipate more heat than a SRAM of comparable memory density. Thus efficient lower-power SRAM device designs are particularly suitable for VLSI systems having need for high-density components, providing those memory components observe the often strict overall design constraints of the particular VLSI system.
Furthermore, the SRAM subsystems of many VLSI systems frequently are integrated relative to particular design implementations, with specific adaptations of the SRAM subsystem limiting, or even precluding, the scalability of the SRAM subsystem design. As a result SRAM memory subsystem designs, even those considered to be “scalable”, often fail to meet such design limitations once these memory subsystem designs are scaled-up for use in a VLSI system needing a greater memory cell population and/or density.
Accordingly, there is a need for an efficient, scalable, high-performance, low-power synchronous, self-timed memory structure that enables a system designer to create a SRAM memory subsystem that satisfies strict constraints of device area, power, performance, noise sensitivity, and the like.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.